Hardware-efficient quantum error correction via concatenated bosonic qubits

In order to solve problems of practical importance, quantum computers willlikely need to incorporate quantum error correction, where a logical qubit isredundantly encoded in many noisy physical qubits. The large physical-qubitoverhead typically associated with error correction motivates the search formore hardware-efficient approaches. Here, using a microfabricatedsuperconducting quantum circuit, we realize a logical qubit memory formed fromthe concatenation of encoded bosonic cat qubits with an outer repetition codeof distance d=5. The bosonic cat qubits are passively protected against bitflips using a stabilizing circuit. Cat-qubit phase-flip errors are corrected bythe repetition code which uses ancilla transmons for syndrome measurement. Werealize a noise-biased CX gate which ensures bit-flip error suppression ismaintained during error correction. We study the performance and scaling of thelogical qubit memory, finding that the phase-flip correcting repetition codeoperates below threshold, with logical phase-flip error decreasing with codedistance from d=3 to d=5. Concurrently, the logical bit-flip error issuppressed with increasing cat-qubit mean photon number. The minimum measuredlogical error per cycle is on average 1.75(2)% for the distance-3 codesections, and 1.65(3)% for the longer distance-5 code, demonstrating theeffectiveness of bit-flip error suppression throughout the error correctioncycle. These results, where the intrinsic error suppression of the bosonicencodings allows us to use a hardware-efficient outer error correcting code,indicate that concatenated bosonic codes are a compelling paradigm for reachingfault-tolerant quantum computation.

Further reading#

• Access Paper in arXiv.org